1. Field of the Invention
The present invention relates to controlling asynchronous data transfer and more particularly to an interlock circuit and method for controlling data transfer between a host processor and a plurality of microprocessors through a common buffer.
2. Description of the Prior Art
For operation of a multi-processor system, it is necessary that a host processor communicate with each of its associated microprocessors and each microprocessor communicate with the host processor. Such communication between these processors takes the form of data transfers through a common buffer. A common buffer is utilized so that economical and efficient use of the system's resources may be made. However, in such a system each processor may simultaneously transmit data to another processor thereby, producing mixing and destruction of the data. In addition, this process is further complicated by the transmission of data words of varying length. For example, the INTEL Model 8080 microprocessor CPU is a single LSI chip of silicon gate MOS technology with a word size of 8-bits whereas, a suitable host processor (mini-computer or large-scale computer) typically has word lengths of 16 bits or more.
One such system is taught by U.S. Pat. No. 3,976,979 issued on Aug. 24, 1976, to K. L. Parkinson, et al. Shown is a host processor coupled to a single remote processor. In such a system, data is transmitted by one processor and received by the other processor. The addition and control of other remote processors is not taught by Parkinson.
Therefore, it is the object of the present invention to provide for an interlock control circuit and control method of bidirectional asynchronous data transfer between a plurality of microprocessors and a host processor. In addition, it is an objective of the present invention to provide the capability for a host processor to terminate any processor's data transfer.
It is a further objective of the invention to provide the above-mentioned features in a manner so that the number of microprocessors employed may be expanded economically and with a minimum of alterations of the interlock control circuit.